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| author | Dan Gohman <gohman@apple.com> | 2009-04-27 16:33:14 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-04-27 16:33:14 +0000 |
| commit | ec542ca65e1f3825fc2a375c608d1924a6fb0de5 (patch) | |
| tree | 445f7ea3528229d03c89ab56df7aa6a4dbee5023 /llvm/lib/Target/X86/X86InstrInfo.cpp | |
| parent | ba99bddf1f1b1593a9666ab86aac7a390e7dbb14 (diff) | |
| download | bcm5719-llvm-ec542ca65e1f3825fc2a375c608d1924a6fb0de5.tar.gz bcm5719-llvm-ec542ca65e1f3825fc2a375c608d1924a6fb0de5.zip | |
Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.
llvm-svn: 70210
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index d8c0833981a..e748e11b932 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -1681,13 +1681,13 @@ bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, Opc = X86::MOV8rr_NOREX; else Opc = X86::MOV8rr; - } else if (CommonRC == &X86::GR64_RegClass) { + } else if (CommonRC == &X86::GR64_ABCDRegClass) { Opc = X86::MOV64rr; - } else if (CommonRC == &X86::GR32_RegClass) { + } else if (CommonRC == &X86::GR32_ABCDRegClass) { Opc = X86::MOV32rr; - } else if (CommonRC == &X86::GR16_RegClass) { + } else if (CommonRC == &X86::GR16_ABCDRegClass) { Opc = X86::MOV16rr; - } else if (CommonRC == &X86::GR8_RegClass) { + } else if (CommonRC == &X86::GR8_ABCDRegClass) { Opc = X86::MOV8rr; } else if (CommonRC == &X86::GR64_NOREXRegClass) { Opc = X86::MOV64rr; @@ -1802,13 +1802,13 @@ static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, Opc = X86::MOV16mr; } else if (RC == &X86::GR8RegClass) { Opc = X86::MOV8mr; - } else if (RC == &X86::GR64_RegClass) { + } else if (RC == &X86::GR64_ABCDRegClass) { Opc = X86::MOV64mr; - } else if (RC == &X86::GR32_RegClass) { + } else if (RC == &X86::GR32_ABCDRegClass) { Opc = X86::MOV32mr; - } else if (RC == &X86::GR16_RegClass) { + } else if (RC == &X86::GR16_ABCDRegClass) { Opc = X86::MOV16mr; - } else if (RC == &X86::GR8_RegClass) { + } else if (RC == &X86::GR8_ABCDRegClass) { Opc = X86::MOV8mr; } else if (RC == &X86::GR64_NOREXRegClass) { Opc = X86::MOV64mr; @@ -1882,13 +1882,13 @@ static unsigned getLoadRegOpcode(const TargetRegisterClass *RC, Opc = X86::MOV16rm; } else if (RC == &X86::GR8RegClass) { Opc = X86::MOV8rm; - } else if (RC == &X86::GR64_RegClass) { + } else if (RC == &X86::GR64_ABCDRegClass) { Opc = X86::MOV64rm; - } else if (RC == &X86::GR32_RegClass) { + } else if (RC == &X86::GR32_ABCDRegClass) { Opc = X86::MOV32rm; - } else if (RC == &X86::GR16_RegClass) { + } else if (RC == &X86::GR16_ABCDRegClass) { Opc = X86::MOV16rm; - } else if (RC == &X86::GR8_RegClass) { + } else if (RC == &X86::GR8_ABCDRegClass) { Opc = X86::MOV8rm; } else if (RC == &X86::GR64_NOREXRegClass) { Opc = X86::MOV64rm; |
