diff options
| author | Craig Topper <craig.topper@intel.com> | 2017-12-10 17:42:39 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-10 17:42:39 +0000 |
| commit | aa904d5ab6f3938a0f1f1d3439f77be1ea2ea909 (patch) | |
| tree | c4db695f66a41cd8ae4007753f04238a3db49650 /llvm/lib/Target/X86/X86InstrInfo.cpp | |
| parent | 7c89de1760f815c38c622fc1cca58de09f14f160 (diff) | |
| download | bcm5719-llvm-aa904d5ab6f3938a0f1f1d3439f77be1ea2ea909.tar.gz bcm5719-llvm-aa904d5ab6f3938a0f1f1d3439f77be1ea2ea909.zip | |
[X86] Fix a few instructions that were named Z512 instead of just Z.
This makes things consistent with our normal instruction naming.
llvm-svn: 320316
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 51ccc178e1a..68a7bb2e5c1 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -977,14 +977,14 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VPSHUFDZri, X86::VPSHUFDZmi, 0 }, { X86::VPSHUFHWZri, X86::VPSHUFHWZmi, 0 }, { X86::VPSHUFLWZri, X86::VPSHUFLWZmi, 0 }, - { X86::VPSLLDQZ512rr, X86::VPSLLDQZ512rm, 0 }, + { X86::VPSLLDQZrr, X86::VPSLLDQZrm, 0 }, { X86::VPSLLDZri, X86::VPSLLDZmi, 0 }, { X86::VPSLLQZri, X86::VPSLLQZmi, 0 }, { X86::VPSLLWZri, X86::VPSLLWZmi, 0 }, { X86::VPSRADZri, X86::VPSRADZmi, 0 }, { X86::VPSRAQZri, X86::VPSRAQZmi, 0 }, { X86::VPSRAWZri, X86::VPSRAWZmi, 0 }, - { X86::VPSRLDQZ512rr, X86::VPSRLDQZ512rm, 0 }, + { X86::VPSRLDQZrr, X86::VPSRLDQZrm, 0 }, { X86::VPSRLDZri, X86::VPSRLDZmi, 0 }, { X86::VPSRLQZri, X86::VPSRLQZmi, 0 }, { X86::VPSRLWZri, X86::VPSRLWZmi, 0 }, @@ -2042,7 +2042,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 }, { X86::VPORDZrr, X86::VPORDZrm, 0 }, { X86::VPORQZrr, X86::VPORQZrm, 0 }, - { X86::VPSADBWZ512rr, X86::VPSADBWZ512rm, 0 }, + { X86::VPSADBWZrr, X86::VPSADBWZrm, 0 }, { X86::VPSHUFBZrr, X86::VPSHUFBZrm, 0 }, { X86::VPSLLDZrr, X86::VPSLLDZrm, 0 }, { X86::VPSLLQZrr, X86::VPSLLQZrm, 0 }, |
