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| author | Hans Wennborg <hans@hanshq.net> | 2017-12-04 22:21:15 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2017-12-04 22:21:15 +0000 |
| commit | 361d4392cf5425bf560f88895f22df61b273fe4e (patch) | |
| tree | 1f6eedd1e5af96360da68cd45d7137a054e30286 /llvm/lib/Target/X86/X86InstrInfo.cpp | |
| parent | 68f05052638e11164bc88cd4022ad78d8ad72306 (diff) | |
| download | bcm5719-llvm-361d4392cf5425bf560f88895f22df61b273fe4e.tar.gz bcm5719-llvm-361d4392cf5425bf560f88895f22df61b273fe4e.zip | |
Revert r319490 "XOR the frame pointer with the stack cookie when protecting the stack"
This broke the Chromium build (crbug.com/791714). Reverting while investigating.
> Summary: This strengthens the guard and matches MSVC.
>
> Reviewers: hans, etienneb
>
> Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D40622
>
> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319490 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-svn: 319706
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 96f19d35815..a5bff06e70b 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -7762,18 +7762,6 @@ static void expandLoadStackGuard(MachineInstrBuilder &MIB, MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0); } -static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) { - MachineBasicBlock &MBB = *MIB->getParent(); - MachineFunction &MF = *MBB.getParent(); - const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); - const X86RegisterInfo *TRI = Subtarget.getRegisterInfo(); - unsigned XorOp = - MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr; - MIB->setDesc(TII.get(XorOp)); - MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef); - return true; -} - // This is used to handle spills for 128/256-bit registers when we have AVX512, // but not VLX. If it uses an extended register we need to use an instruction // that loads the lower 128/256-bit, but is available with only AVX512F. @@ -7968,9 +7956,6 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case TargetOpcode::LOAD_STACK_GUARD: expandLoadStackGuard(MIB, *this); return true; - case X86::XOR64_FP: - case X86::XOR32_FP: - return expandXorFP(MIB, *this); } return false; } |

