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| author | Craig Topper <craig.topper@gmail.com> | 2017-01-26 07:17:53 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-01-26 07:17:53 +0000 |
| commit | f0bab7b7395970fbd4ce3600731f932c89d3000b (patch) | |
| tree | a9a0309507900b0919bcab4af9979340801f521c /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 8e2f948ef04472e1e8a28ef6d02e29deebe7d1c6 (diff) | |
| download | bcm5719-llvm-f0bab7b7395970fbd4ce3600731f932c89d3000b.tar.gz bcm5719-llvm-f0bab7b7395970fbd4ce3600731f932c89d3000b.zip | |
[X86] When bitcasting INSERT_SUBVECTOR/EXTRACT_SUBVECTOR to match masked operations, use the correct type for the immediate operand.
llvm-svn: 293156
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c6ef240b9b1..79e58ba4b03 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -29096,7 +29096,7 @@ static bool combineBitcastForMaskedOp(SDValue OrigOp, SelectionDAG &DAG, DCI.AddToWorklist(Op1.getNode()); DCI.CombineTo(OrigOp.getNode(), DAG.getNode(Opcode, DL, VT, Op0, Op1, - DAG.getConstant(Imm, DL, MVT::i8))); + DAG.getIntPtrConstant(Imm, DL))); return true; } case ISD::EXTRACT_SUBVECTOR: { @@ -29117,7 +29117,7 @@ static bool combineBitcastForMaskedOp(SDValue OrigOp, SelectionDAG &DAG, DCI.AddToWorklist(Op0.getNode()); DCI.CombineTo(OrigOp.getNode(), DAG.getNode(Opcode, DL, VT, Op0, - DAG.getConstant(Imm, DL, MVT::i8))); + DAG.getIntPtrConstant(Imm, DL))); return true; } case X86ISD::SUBV_BROADCAST: { |
