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authorCraig Topper <craig.topper@intel.com>2019-09-03 02:51:10 +0000
committerCraig Topper <craig.topper@intel.com>2019-09-03 02:51:10 +0000
commitdcecc7ea468d62dda89bd7666001a1412dae6345 (patch)
treede6b19cc216709dfacccf1d7722e2ce31611650c /llvm/lib/Target/X86/X86ISelLowering.cpp
parentdea9cad10e02e12ecb1705bca4c4244208891230 (diff)
downloadbcm5719-llvm-dcecc7ea468d62dda89bd7666001a1412dae6345.tar.gz
bcm5719-llvm-dcecc7ea468d62dda89bd7666001a1412dae6345.zip
[X86] Custom promote i32->f80 uint_to_fp on AVX512 64-bit targets.
Reuse the same code to promote all i32 uint_to_fp on 64-bit targets to simplify the X86ISelLowering constructor. llvm-svn: 370693
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp15
1 files changed, 7 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f29d50fccb2..6f0fb3ac97b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -221,14 +221,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
- if (Subtarget.is64Bit()) {
- if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
- // f32/f64 are legal, f80 is custom.
- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
- else
- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
- setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
- } else if (!Subtarget.useSoftFloat()) {
+ if (!Subtarget.useSoftFloat()) {
// We have an algorithm for SSE2->double, and we turn this into a
// 64-bit FILD followed by conditional FADD for other targets.
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
@@ -18657,6 +18650,12 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
return Op;
}
+ // Promote i32 to i64 and use a signed conversion on 64-bit targets.
+ if (SrcVT == MVT::i32 && Subtarget.is64Bit()) {
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, N0);
+ return DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, N0);
+ }
+
if (SDValue V = LowerI64IntToFP_AVX512DQ(Op, DAG, Subtarget))
return V;
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