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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-09-26 14:12:50 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-09-26 14:12:50 +0000 |
| commit | dac6fd41704ba16c39584183895079032e7bb99a (patch) | |
| tree | 7b2e4ec7e1a0de7f819cf73fd17e74a788e3e7b1 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 1d04b5bacf4fab305db930895a543dc42614b81f (diff) | |
| download | bcm5719-llvm-dac6fd41704ba16c39584183895079032e7bb99a.tar.gz bcm5719-llvm-dac6fd41704ba16c39584183895079032e7bb99a.zip | |
[X86][XOP] Merge rotation opcodes with AVX512 equivalents. NFCI.
The XOP rotations act as ROTL with +ve values and ROTR with -ve values, which means that we can treat them all as ROTL with unsigned modulo. We already check that we're only trying to lower as ROTL for XOP rotations.
Differential Revision: https://reviews.llvm.org/D37949
llvm-svn: 314207
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0d7dfe76908..02e8f9d7cb4 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -22667,7 +22667,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget, assert((Opcode == ISD::ROTL) && "Only ROTL supported"); // XOP has 128-bit vector variable + immediate rotates. - // +ve/-ve Amt = rotate left/right. + // +ve/-ve Amt = rotate left/right - just need to handle ISD::ROTL. // Split 256-bit integers. if (VT.is256BitVector()) @@ -22680,13 +22680,13 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget, if (auto *RotateConst = BVAmt->getConstantSplatNode()) { uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue(); assert(RotateAmt < EltSizeInBits && "Rotation out of range"); - return DAG.getNode(X86ISD::VPROTI, DL, VT, R, + return DAG.getNode(X86ISD::VROTLI, DL, VT, R, DAG.getConstant(RotateAmt, DL, MVT::i8)); } } // Use general rotate by variable (per-element). - return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt); + return Op; } static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) { @@ -24610,8 +24610,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::RDSEED: return "X86ISD::RDSEED"; case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW"; case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD"; - case X86ISD::VPROT: return "X86ISD::VPROT"; - case X86ISD::VPROTI: return "X86ISD::VPROTI"; case X86ISD::VPSHA: return "X86ISD::VPSHA"; case X86ISD::VPSHL: return "X86ISD::VPSHL"; case X86ISD::VPCOM: return "X86ISD::VPCOM"; |
