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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-08-06 09:46:13 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-08-06 09:46:13 +0000 |
| commit | ced419f4d76a2f8bcd8647f0792e0fc20ad351ed (patch) | |
| tree | 82137fa963f565c842a733ad148b438ff2b85126 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 1eb84c4d063483218abcc8970548e9ac0cb691e1 (diff) | |
| download | bcm5719-llvm-ced419f4d76a2f8bcd8647f0792e0fc20ad351ed.tar.gz bcm5719-llvm-ced419f4d76a2f8bcd8647f0792e0fc20ad351ed.zip | |
[SelectionDAG] Extend base addressing modes supported by MGATHER/MSCATTER
Summary:
Before this patch MGATHER/MSCATTER is capable of representing all
common addressing modes, but only when illegal types are used.
This patch adds an IndexType property so more representations
are available when using legal types only.
Original modes:
vector of bases
base + vector of signed scaled offsets
New modes:
base + vector of signed unscaled offsets
base + vector of unsigned scaled offsets
base + vector of unsigned unscaled offsets
The current behaviour of addressing modes for gather/scatter remains
unchanged.
Patch by Paul Walker.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D65636
llvm-svn: 368008
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4e162951fbf..939fecf2bc5 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -27071,7 +27071,7 @@ static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget &Subtarget, DAG.getConstant(0, dl, MVT::v2i1)); SDValue Ops[] = {Chain, Src, Mask, BasePtr, Index, Scale}; return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), N->getMemoryVT(), dl, - Ops, N->getMemOperand()); + Ops, N->getMemOperand(), N->getIndexType()); } MVT IndexVT = Index.getSimpleValueType(); @@ -28297,7 +28297,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, Gather->getBasePtr(), Index, Gather->getScale() }; SDValue Res = DAG.getMaskedGather(DAG.getVTList(MVT::v4i32, MVT::Other), Gather->getMemoryVT(), dl, Ops, - Gather->getMemOperand()); + Gather->getMemOperand(), + Gather->getIndexType()); SDValue Chain = Res.getValue(1); if (getTypeAction(*DAG.getContext(), MVT::v2i32) != TypeWidenVector) Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, |
