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| author | Alex Bradbury <asb@lowrisc.org> | 2018-10-03 20:12:10 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-10-03 20:12:10 +0000 |
| commit | ce9049952fa253791397028e88f3bcad3a7b87e6 (patch) | |
| tree | ac02590f9c5f8ca6ef4f7ea8b66c2da8afe0199a /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 6bdf63bd329d1bb5e48acbb8f25ee0ea8fecd9e2 (diff) | |
| download | bcm5719-llvm-ce9049952fa253791397028e88f3bcad3a7b87e6.tar.gz bcm5719-llvm-ce9049952fa253791397028e88f3bcad3a7b87e6.zip | |
[RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection
Although we can't write a tablegen pattern to remove redundant
splitf64+buildf64 pairs due to the multiple return values, we can handle it
with some C++ selection code. This is simpler than removing them after
instruction selection through RISCVDAGToDAGISel::PostprocessISelDAG, as was
done previously.
llvm-svn: 343712
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
0 files changed, 0 insertions, 0 deletions
