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authorEvan Cheng <evan.cheng@apple.com>2006-01-27 08:10:46 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-01-27 08:10:46 +0000
commitcde9e30bc6acdb22b21e1553f3460a9ab5363e62 (patch)
tree65bc1e66103cfe4eed9bd4255f3120a9d03581a9 /llvm/lib/Target/X86/X86ISelLowering.cpp
parentd98701c639f6786b39754bd0de75181c7ad2f24e (diff)
downloadbcm5719-llvm-cde9e30bc6acdb22b21e1553f3460a9ab5363e62.tar.gz
bcm5719-llvm-cde9e30bc6acdb22b21e1553f3460a9ab5363e62.zip
x86 CPU detection and proper subtarget support
llvm-svn: 25679
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 067b88c9114..cd014aa3319 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33,6 +33,9 @@ static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
X86TargetLowering::X86TargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
+ Subtarget = &TM.getSubtarget<X86Subtarget>();
+ X86ScalarSSE = Subtarget->hasSSE2();
+
// Set up the TargetLowering object.
// X86 is weird, it always uses i8 for shift amounts and setcc results.
@@ -1657,8 +1660,8 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::SELECT: {
MVT::ValueType VT = Op.getValueType();
bool isFP = MVT::isFloatingPoint(VT);
- bool isFPStack = isFP && (X86Vector < SSE2);
- bool isFPSSE = isFP && (X86Vector >= SSE2);
+ bool isFPStack = isFP && !X86ScalarSSE;
+ bool isFPSSE = isFP && X86ScalarSSE;
bool addTest = false;
SDOperand Op0 = Op.getOperand(0);
SDOperand Cond, CC;
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