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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-06-01 05:31:59 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-06-01 05:31:59 +0000 |
commit | bd7d80a4a6b70bf303fd9344d3e70bbe1420062a (patch) | |
tree | 1aa6a8e53ce6145eb05260d2c74335ac3c244dd2 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
parent | 0dba2b399e1cd331f70002f6b922e45bda2b5c2c (diff) | |
download | bcm5719-llvm-bd7d80a4a6b70bf303fd9344d3e70bbe1420062a.tar.gz bcm5719-llvm-bd7d80a4a6b70bf303fd9344d3e70bbe1420062a.zip |
Add address space argument to isLegalAddressingMode
This is important because of different addressing modes
depending on the address space for GPU targets.
This only adds the argument, and does not update
any of the uses to provide the correct address space.
llvm-svn: 238723
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 85884912606..3822dc0a732 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18269,7 +18269,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { // isLegalAddressingMode - Return true if the addressing mode represented // by AM is legal for this target, for a load/store of the specified type. bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, - Type *Ty) const { + Type *Ty, + unsigned AS) const { // X86 supports extremely general addressing modes. CodeModel::Model M = getTargetMachine().getCodeModel(); Reloc::Model R = getTargetMachine().getRelocationModel(); @@ -25405,7 +25406,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, } int X86TargetLowering::getScalingFactorCost(const AddrMode &AM, - Type *Ty) const { + Type *Ty, + unsigned AS) const { // Scaling factors are not free at all. // An indexed folded instruction, i.e., inst (reg1, reg2, scale), // will take 2 allocations in the out of order engine instead of 1 @@ -25424,7 +25426,7 @@ int X86TargetLowering::getScalingFactorCost(const AddrMode &AM, // E.g., on Haswell: // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3. // vmovaps %ymm1, (%r8) can use port 2, 3, or 7. - if (isLegalAddressingMode(AM, Ty)) + if (isLegalAddressingMode(AM, Ty, AS)) // Scale represents reg2 * scale, thus account for 1 // as soon as we use a second register. return AM.Scale != 0; |