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authorEvan Cheng <evan.cheng@apple.com>2006-08-11 09:08:15 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-08-11 09:08:15 +0000
commitbd1c5a8fb8d03d5a9052fc68980ab1306e0080ec (patch)
tree69611ab5eb2f4b0f38db5f17050ec3f04ebb6b63 /llvm/lib/Target/X86/X86ISelLowering.cpp
parent81b645a76b2129f9645273e7e6a13c458d0ddcf9 (diff)
downloadbcm5719-llvm-bd1c5a8fb8d03d5a9052fc68980ab1306e0080ec.tar.gz
bcm5719-llvm-bd1c5a8fb8d03d5a9052fc68980ab1306e0080ec.zip
Match tablegen changes.
llvm-svn: 29604
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp32
1 files changed, 24 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4b074700225..69b3dea0302 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2992,9 +2992,14 @@ SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
}
Constant *CS = ConstantStruct::get(CV);
SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
- SDOperand Mask
- = DAG.getNode(X86ISD::LOAD_PACK,
- VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+ std::vector<MVT::ValueType> Tys;
+ Tys.push_back(VT);
+ Tys.push_back(MVT::Other);
+ SmallVector<SDOperand, 3> Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(CPIdx);
+ Ops.push_back(DAG.getSrcValue(NULL));
+ SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
}
@@ -3013,8 +3018,14 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
}
Constant *CS = ConstantStruct::get(CV);
SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
- SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK,
- VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+ std::vector<MVT::ValueType> Tys;
+ Tys.push_back(VT);
+ Tys.push_back(MVT::Other);
+ SmallVector<SDOperand, 3> Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(CPIdx);
+ Ops.push_back(DAG.getSrcValue(NULL));
+ SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
}
@@ -4121,10 +4132,15 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
Base->getOperand(2));
else {
// Just use movups, it's shorter.
+ std::vector<MVT::ValueType> Tys;
+ Tys.push_back(MVT::v4f32);
+ Tys.push_back(MVT::Other);
+ SmallVector<SDOperand, 3> Ops;
+ Ops.push_back(Base->getOperand(0));
+ Ops.push_back(Base->getOperand(1));
+ Ops.push_back(Base->getOperand(2));
return DAG.getNode(ISD::BIT_CONVERT, VT,
- DAG.getNode(X86ISD::LOAD_UA, MVT::v4f32,
- Base->getOperand(0), Base->getOperand(1),
- Base->getOperand(2)));
+ DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
}
}
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