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authorCraig Topper <craig.topper@intel.com>2017-10-02 05:46:52 +0000
committerCraig Topper <craig.topper@intel.com>2017-10-02 05:46:52 +0000
commitbb7866162cb0b63d75eb6eae1fa9ea6fca38aa37 (patch)
tree9dda003b78c7441d8e45f76a2879f01bc302479a /llvm/lib/Target/X86/X86ISelLowering.cpp
parent806b8d56a2b28e7f16945cfa78affb9fdce16179 (diff)
downloadbcm5719-llvm-bb7866162cb0b63d75eb6eae1fa9ea6fca38aa37.tar.gz
bcm5719-llvm-bb7866162cb0b63d75eb6eae1fa9ea6fca38aa37.zip
[X86] Use a bool flag instead of assigning an unsigned to two different values that we only use in an equality comparison.
llvm-svn: 314647
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp17
1 files changed, 8 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6abf46f470f..616519941fc 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22341,7 +22341,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
// the vector shift into four scalar shifts plus four pairs of vector
// insert/extract.
if (ConstantAmt && (VT == MVT::v8i16 || VT == MVT::v4i32)) {
- unsigned TargetOpcode = X86ISD::MOVSS;
+ bool UseMOVSD = false;
bool CanBeSimplified;
// The splat value for the first packed shift (the 'X' from the example).
SDValue Amt1 = Amt->getOperand(0);
@@ -22358,7 +22358,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
// Otherwise, check if we can still simplify this node using a MOVSD.
CanBeSimplified = Amt1 == Amt->getOperand(1) &&
Amt->getOperand(2) == Amt->getOperand(3);
- TargetOpcode = X86ISD::MOVSD;
+ UseMOVSD = true;
Amt2 = Amt->getOperand(2);
}
} else {
@@ -22369,7 +22369,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
CanBeSimplified = Amt2 == Amt->getOperand(i);
if (!CanBeSimplified) {
- TargetOpcode = X86ISD::MOVSD;
+ UseMOVSD = true;
CanBeSimplified = true;
Amt2 = Amt->getOperand(4);
for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
@@ -22382,19 +22382,18 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
isa<ConstantSDNode>(Amt2)) {
// Replace this node with two shifts followed by a MOVSS/MOVSD/PBLEND.
- MVT CastVT = MVT::v4i32;
SDValue Splat1 =
DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
SDValue Splat2 =
DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
- SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
- SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
- if (TargetOpcode == X86ISD::MOVSD)
- return DAG.getBitcast(VT, DAG.getVectorShuffle(CastVT, dl, BitCast1,
+ SDValue BitCast1 = DAG.getBitcast(MVT::v4i32, Shift1);
+ SDValue BitCast2 = DAG.getBitcast(MVT::v4i32, Shift2);
+ if (UseMOVSD)
+ return DAG.getBitcast(VT, DAG.getVectorShuffle(MVT::v4i32, dl, BitCast1,
BitCast2, {0, 1, 6, 7}));
- return DAG.getBitcast(VT, DAG.getVectorShuffle(CastVT, dl, BitCast1,
+ return DAG.getBitcast(VT, DAG.getVectorShuffle(MVT::v4i32, dl, BitCast1,
BitCast2, {0, 5, 6, 7}));
}
}
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