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| author | Eli Friedman <eli.friedman@gmail.com> | 2011-07-29 03:05:32 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2011-07-29 03:05:32 +0000 |
| commit | adec587d5cbed8860e70f16e6469b9446c45492a (patch) | |
| tree | 0f0a2560825b68ba4fbbde6cc8d3dad2a2eb4ed0 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 0978426843672d8e3da40d2cde36b7d846f76ecd (diff) | |
| download | bcm5719-llvm-adec587d5cbed8860e70f16e6469b9446c45492a.tar.gz bcm5719-llvm-adec587d5cbed8860e70f16e6469b9446c45492a.zip | |
Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to be
working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)
llvm-svn: 136457
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5987e57a693..abfc6e29aa9 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -9562,7 +9562,9 @@ SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { Node->getOperand(0), Node->getOperand(1), negOp, cast<AtomicSDNode>(Node)->getSrcValue(), - cast<AtomicSDNode>(Node)->getAlignment()); + cast<AtomicSDNode>(Node)->getAlignment(), + cast<AtomicSDNode>(Node)->getOrdering(), + cast<AtomicSDNode>(Node)->getSynchScope()); } static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { |
