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| author | Craig Topper <craig.topper@intel.com> | 2018-02-19 19:23:31 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-19 19:23:31 +0000 |
| commit | 9471a7c89855ad591ce9178ead5fa59b92de9e45 (patch) | |
| tree | 162dad66b674fa649a5494e44406c594f955a5ed /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 545d34a2724ef158d79c5e37dc817ceea9fbd1d8 (diff) | |
| download | bcm5719-llvm-9471a7c89855ad591ce9178ead5fa59b92de9e45.tar.gz bcm5719-llvm-9471a7c89855ad591ce9178ead5fa59b92de9e45.zip | |
[X86] Reduce the number of isel pattern variations needed for VPTESTM/VPTESTNM matching.
Canonicalize EQ/NE PCMPM to have build vector all zeros on the RHS so we don't have to pattern match it in both locations. This significantly reduces the number of isel patterns needed since we also had to multiply it out with loads being in either operand of the 'and' input node and in the 'and' masking node.
This removes over 24000 bytes from the isel table.
llvm-svn: 325526
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9f483b72a89..2f2ae32a1d1 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17830,6 +17830,14 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) { "Cannot set masked compare for this operation"); ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); + + // If this is a seteq make sure any build vectors of all zeros are on the RHS. + // This helps with vptestm matching. + // TODO: Should we just canonicalize the setcc during DAG combine? + if ((SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE) && + ISD::isBuildVectorAllZeros(Op0.getNode())) + std::swap(Op0, Op1); + bool Swap = false; unsigned SSECC; switch (SetCCOpcode) { |
