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authorSimon Pilgrim <llvm-dev@redking.me.uk>2016-08-24 12:42:31 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2016-08-24 12:42:31 +0000
commit7a50c8c2ba58beaa70879d22c628ebd213fcf4ee (patch)
tree225fd7c993376e510b7527341f8fd87097b7a95f /llvm/lib/Target/X86/X86ISelLowering.cpp
parent3c8cd3df5e87e7549202af7f1b404ec0d106ecb1 (diff)
downloadbcm5719-llvm-7a50c8c2ba58beaa70879d22c628ebd213fcf4ee.tar.gz
bcm5719-llvm-7a50c8c2ba58beaa70879d22c628ebd213fcf4ee.zip
[X86][AVX2] Ensure on 32-bit targets that we broadcast f64 types not i64 (PR29101)
llvm-svn: 279622
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 105b02dea71..293d5a4ac14 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8733,6 +8733,13 @@ static SDValue lowerVectorShuffleAsBroadcast(const SDLoc &DL, MVT VT,
V = DAG.getBitcast(SrcVT, V);
}
+ // 32-bit targets need to load i64 as a f64 and then bitcast the result.
+ if (!Subtarget.is64Bit() && SrcVT == MVT::i64) {
+ V = DAG.getBitcast(MVT::f64, V);
+ unsigned NumBroadcastElts = BroadcastVT.getVectorNumElements();
+ BroadcastVT = MVT::getVectorVT(MVT::f64, NumBroadcastElts);
+ }
+
return DAG.getBitcast(VT, DAG.getNode(Opcode, DL, BroadcastVT, V));
}
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