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| author | Craig Topper <craig.topper@intel.com> | 2017-09-03 22:25:49 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-03 22:25:49 +0000 |
| commit | 788fbe08db9c557f8a445540a197e1e9d9c31493 (patch) | |
| tree | 0c632886a268c93f1f310f8489d834e8ba559758 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | d8f067539b5733a9dbddeb8dc2e488aee76f1aa6 (diff) | |
| download | bcm5719-llvm-788fbe08db9c557f8a445540a197e1e9d9c31493.tar.gz bcm5719-llvm-788fbe08db9c557f8a445540a197e1e9d9c31493.zip | |
[X86] Combine inserting a vector of zeros into a vector of zeros just the larger vector.
llvm-svn: 312458
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0193f2bfd58..2cb6ec376c4 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -35656,6 +35656,11 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG, unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); MVT SubVecVT = SubVec.getSimpleValueType(); + // Inserting zeros into zeros is a nop. + if (ISD::isBuildVectorAllZeros(Vec.getNode()) && + ISD::isBuildVectorAllZeros(SubVec.getNode())) + return Vec; + // If this is an insert of an extract, combine to a shuffle. Don't do this // if the insert or extract can be represented with a subregister operation. if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && |
