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authorCraig Topper <craig.topper@intel.com>2018-01-14 08:11:33 +0000
committerCraig Topper <craig.topper@intel.com>2018-01-14 08:11:33 +0000
commit57d58051bb24112f86794fba791eea3d6610f629 (patch)
treec7e455f451cf20eea66006205ff35e3584695109 /llvm/lib/Target/X86/X86ISelLowering.cpp
parentfe148c88da263c1dbd9df6a3cf416a7b5278d87a (diff)
downloadbcm5719-llvm-57d58051bb24112f86794fba791eea3d6610f629.tar.gz
bcm5719-llvm-57d58051bb24112f86794fba791eea3d6610f629.zip
[X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.
We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements. Ideally we'd just use ISD::TRUNCATE for these cases instead. llvm-svn: 322454
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f8e0a939983..c1cbb64eeb5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -27837,6 +27837,18 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known.Zero.setBitsFrom(InBitWidth);
break;
}
+ case X86ISD::VTRUNC: {
+ // TODO: Add DemandedElts support.
+ SDValue N0 = Op.getOperand(0);
+ // We can only handle cases with the same number of elements. Otherwise
+ // the truncate fills with zero elements.
+ // TODO: Maybe we could just discard any 1s we found instead of skipping?
+ if (VT.getVectorNumElements() != N0.getValueType().getVectorNumElements())
+ break;
+ DAG.computeKnownBits(N0, Known, Depth+1);
+ Known = Known.trunc(BitWidth);
+ break;
+ }
case X86ISD::CMOV: {
DAG.computeKnownBits(Op.getOperand(1), Known, Depth+1);
// If we don't know any bits, early out.
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