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| author | Devang Patel <dpatel@apple.com> | 2009-01-05 17:31:22 +0000 |
|---|---|---|
| committer | Devang Patel <dpatel@apple.com> | 2009-01-05 17:31:22 +0000 |
| commit | 56a8bb670f9eb91416e867dd4f8670547497fc27 (patch) | |
| tree | 409f18068593ba69f6ea2749bfefa31c7f2edac0 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 1d59d7843cb1f9d0e513be14f6f45b53ba3d7cbb (diff) | |
| download | bcm5719-llvm-56a8bb670f9eb91416e867dd4f8670547497fc27.tar.gz bcm5719-llvm-56a8bb670f9eb91416e867dd4f8670547497fc27.zip | |
squash warnings.
llvm-svn: 61707
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5ed6342bb1b..c282f918ead 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1255,7 +1255,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { if (VA.isRegLoc()) { MVT RegVT = VA.getLocVT(); - TargetRegisterClass *RC; + TargetRegisterClass *RC = NULL; if (RegVT == MVT::i32) RC = X86::GR32RegisterClass; else if (Is64Bit && RegVT == MVT::i64) |
