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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-05-06 20:53:52 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-05-06 20:53:52 +0000
commit33f7397cc0582f3a842cc4cba5fec605c3a09e48 (patch)
treea17458100dbe5cb608981b4f22cedecdf6e3f25e /llvm/lib/Target/X86/X86ISelLowering.cpp
parentc6ad42165f1005ad3b9b3ecb8a63eda3065b15b0 (diff)
downloadbcm5719-llvm-33f7397cc0582f3a842cc4cba5fec605c3a09e48.tar.gz
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[X86][AVX512] Relax assertion and just exit combine for unsupported types (PR32907)
llvm-svn: 302361
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 260dd464cef..8d57b8eecab 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -31638,7 +31638,9 @@ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG,
V = Y;
if (V) {
- assert(EltBits == 8 || EltBits == 16 || EltBits == 32);
+ if (EltBits != 8 && EltBits != 16 && EltBits != 32)
+ return SDValue();
+
SDValue SubOp1 = DAG.getNode(ISD::XOR, DL, MaskVT, V, Mask);
SDValue SubOp2 = Mask;
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