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| author | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
| commit | 295bd43adb9c514c53f6df861ae1c6e97c23a53a (patch) | |
| tree | d13c5eb42f4e12a882379551c8263b927fed7cbe /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 40d7f354b5637066a7ad3d50e19df482ee234d53 (diff) | |
| download | bcm5719-llvm-295bd43adb9c514c53f6df861ae1c6e97c23a53a.tar.gz bcm5719-llvm-295bd43adb9c514c53f6df861ae1c6e97c23a53a.zip | |
The getRegForInlineAsmConstraint function should only accept MVT value types.
llvm-svn: 184642
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7e2e99cfcc4..7db1e474a5c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18423,7 +18423,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::pair<unsigned, const TargetRegisterClass*> X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { + MVT VT) const { // First, see if this is a constraint that directly corresponds to an LLVM // register class. if (Constraint.size() == 1) { @@ -18490,7 +18490,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed if (!Subtarget->hasSSE1()) break; - switch (VT.getSimpleVT().SimpleTy) { + switch (VT.SimpleTy) { default: break; // Scalar SSE types. case MVT::f32: |
