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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-03-11 11:19:19 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-03-11 11:19:19 +0000
commit2565bd421e20e34373041ac4a281947e70748c49 (patch)
tree3cc20f42e1476715c3f2a64edb627d6b920848bd /llvm/lib/Target/X86/X86ISelLowering.cpp
parent1c861c582fbd121ee1db6d9858e443b551a8efc1 (diff)
downloadbcm5719-llvm-2565bd421e20e34373041ac4a281947e70748c49.tar.gz
bcm5719-llvm-2565bd421e20e34373041ac4a281947e70748c49.zip
[X86][AVX512] createVariablePermute - Non-VLX targets can widen v4i64/v8f64 variable permutes to v8i64/v8f64
Permutes in the upper elements will be undefined, but they will be discarded anyway. llvm-svn: 327238
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp14
1 files changed, 12 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index eafa118897a..55c28c3b108 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8048,9 +8048,19 @@ SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec,
break;
case MVT::v4i64:
case MVT::v4f64:
- if (Subtarget.hasVLX())
+ if (Subtarget.hasAVX512()) {
+ if (!Subtarget.hasVLX()) {
+ MVT WidenSrcVT = MVT::getVectorVT(VT.getScalarType(), 8);
+ SrcVec = widenSubVector(WidenSrcVT, SrcVec, false, Subtarget, DAG,
+ SDLoc(SrcVec));
+ IndicesVec = widenSubVector(MVT::v8i64, IndicesVec, false, Subtarget,
+ DAG, SDLoc(IndicesVec));
+ SDValue Res = createVariablePermute(WidenSrcVT, SrcVec, IndicesVec, DL,
+ DAG, Subtarget);
+ return extract256BitVector(Res, 0, DAG, DL);
+ }
Opcode = X86ISD::VPERMV;
- else if (Subtarget.hasXOP()) {
+ } else if (Subtarget.hasXOP()) {
SrcVec = DAG.getBitcast(MVT::v4f64, SrcVec);
SDValue LoLo =
DAG.getVectorShuffle(MVT::v4f64, DL, SrcVec, SrcVec, {0, 1, 0, 1});
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