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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2009-04-07 21:37:46 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2009-04-07 21:37:46 +0000 |
| commit | 1edda06792940406e77b5369c57fe0b468448ec8 (patch) | |
| tree | 6d9bc6b22f58bc5611e01e17730118a607aa1f47 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 9ecb84bb21edb1c4407fae35e149a307e2ba63ad (diff) | |
| download | bcm5719-llvm-1edda06792940406e77b5369c57fe0b468448ec8.tar.gz bcm5719-llvm-1edda06792940406e77b5369c57fe0b468448ec8.zip | |
Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
llvm-svn: 68552
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c5a6acbf7af..6cdc54cfba8 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -4834,8 +4834,13 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT, TLSModel::Model model) { DebugLoc dl = GA->getDebugLoc(); // Get the Thread Pointer - SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, - DebugLoc::getUnknownLoc(), PtrVT); + SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, + DebugLoc::getUnknownLoc(), PtrVT, + DAG.getRegister(X86::GS, MVT::i32)); + + SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, + NULL, 0); + // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial // exec) SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), @@ -7149,7 +7154,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; case X86ISD::FRCP: return "X86ISD::FRCP"; case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; - case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER"; + case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; @@ -7473,7 +7478,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, unsigned t2 = F->getRegInfo().createVirtualRegister(RC); MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); // add 4 to displacement. - for (int i=0; i <= lastAddrIndx-1; ++i) + for (int i=0; i <= lastAddrIndx-2; ++i) (*MIB).addOperand(*argOpers[i]); MachineOperand newOp3 = *(argOpers[3]); if (newOp3.isImm()) @@ -7481,6 +7486,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, else newOp3.setOffset(newOp3.getOffset()+4); (*MIB).addOperand(newOp3); + (*MIB).addOperand(*argOpers[lastAddrIndx]); // t3/4 are defined later, at the bottom of the loop unsigned t3 = F->getRegInfo().createVirtualRegister(RC); |
