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authorEvan Cheng <evan.cheng@apple.com>2009-01-02 05:29:08 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-01-02 05:29:08 +0000
commit1671a309fd407a59b684b708ad00128cf5806c65 (patch)
tree80ef83313b381b465aba2a4206c69edac7ccb9f7 /llvm/lib/Target/X86/X86ISelLowering.cpp
parenta17dfcd58a130667b04df5175cea2f1c110f30d7 (diff)
downloadbcm5719-llvm-1671a309fd407a59b684b708ad00128cf5806c65.tar.gz
bcm5719-llvm-1671a309fd407a59b684b708ad00128cf5806c65.zip
Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory.
llvm-svn: 61555
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 43a7bb5bb5b..5ed6342bb1b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4215,6 +4215,14 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
} else if (VT.getSizeInBits() == 16) {
+ unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+ // If Idx is 0, it's cheaper to do a move instead of a pextrw.
+ if (Idx == 0)
+ return DAG.getNode(ISD::TRUNCATE, MVT::i16,
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
+ DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
+ Op.getOperand(0)),
+ Op.getOperand(1)));
SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
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