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| author | Craig Topper <craig.topper@intel.com> | 2017-11-26 21:14:48 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-26 21:14:48 +0000 |
| commit | 074003c8e22d5d6c0ee7d6e38e78e9b5832b22dc (patch) | |
| tree | 16b9aaf619178e96925d997d41082dcbc6795b17 /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | fe6e92d5172a0579ec8bb10c1d6e4255de3fce81 (diff) | |
| download | bcm5719-llvm-074003c8e22d5d6c0ee7d6e38e78e9b5832b22dc.tar.gz bcm5719-llvm-074003c8e22d5d6c0ee7d6e38e78e9b5832b22dc.zip | |
[X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.
The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert.
llvm-svn: 319006
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 892c7e24abd..5f4e4d7a113 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2149,8 +2149,7 @@ static void Passv64i1ArgInRegs( const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) { - assert((Subtarget.hasBWI() || Subtarget.hasBMI()) && - "Expected AVX512BW or AVX512BMI target!"); + assert(Subtarget.hasBWI() && "Expected AVX512BW target!"); assert(Subtarget.is32Bit() && "Expecting 32 bit target"); assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value"); assert(VA.isRegLoc() && NextVA.isRegLoc() && |
