diff options
| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2012-01-12 20:33:10 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2012-01-12 20:33:10 +0000 |
| commit | 060f6ccdb84a9d6b862f548aebd94884fb6ba77c (patch) | |
| tree | e1ab9be6b1e5f14a535a12b530e413190d302ffe /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 5c03a6b8f59399d524621600e845b7715b7ce969 (diff) | |
| download | bcm5719-llvm-060f6ccdb84a9d6b862f548aebd94884fb6ba77c.tar.gz bcm5719-llvm-060f6ccdb84a9d6b862f548aebd94884fb6ba77c.zip | |
Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed.
Added a test.
llvm-svn: 148044
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c643cefb6c0..6a5e6f5f240 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -6464,6 +6464,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); unsigned NumElems = VT.getVectorNumElements(); + bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; bool V1IsSplat = false; bool V2IsSplat = false; @@ -6475,7 +6476,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); - assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef"); + if (V1IsUndef && V2IsUndef) + return DAG.getUNDEF(VT); + + assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); // Vector shuffle lowering takes 3 steps: // |
