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| author | Evan Cheng <evan.cheng@apple.com> | 2009-01-17 07:09:27 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-01-17 07:09:27 +0000 |
| commit | bf38a5e540b36ef30ac7e60e5d8a3d84184fffe1 (patch) | |
| tree | 5015114917b7e5ba000aa7dcbb9f0342a39c7d84 /llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | |
| parent | bf7d432ce465b0cb88342a1e1b4eb1df0a575bdd (diff) | |
| download | bcm5719-llvm-bf38a5e540b36ef30ac7e60e5d8a3d84184fffe1.tar.gz bcm5719-llvm-bf38a5e540b36ef30ac7e60e5d8a3d84184fffe1.zip | |
Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode.
llvm-svn: 62413
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelDAGToDAG.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 44c43a2ef86..842bb13ae82 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -817,7 +817,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, AM.IndexReg = ShVal.getNode()->getOperand(0); ConstantSDNode *AddVal = cast<ConstantSDNode>(ShVal.getNode()->getOperand(1)); - uint64_t Disp = AM.Disp + (AddVal->getZExtValue() << Val); + uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val); if (!is64Bit || isInt32(Disp)) AM.Disp = Disp; else @@ -858,7 +858,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, Reg = MulVal.getNode()->getOperand(0); ConstantSDNode *AddVal = cast<ConstantSDNode>(MulVal.getNode()->getOperand(1)); - uint64_t Disp = AM.Disp + AddVal->getZExtValue() * + uint64_t Disp = AM.Disp + AddVal->getSExtValue() * CN->getZExtValue(); if (!is64Bit || isInt32(Disp)) AM.Disp = Disp; @@ -874,19 +874,18 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, } break; - case ISD::ADD: - { - X86ISelAddressMode Backup = AM; - if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) && - !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1)) - return false; - AM = Backup; - if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) && - !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1)) - return false; - AM = Backup; - } + case ISD::ADD: { + X86ISelAddressMode Backup = AM; + if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) && + !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1)) + return false; + AM = Backup; + if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) && + !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1)) + return false; + AM = Backup; break; + } case ISD::OR: // Handle "X | C" as "X + C" iff X is known to have C bits clear. |
