add a SelectionDAG method to check if no common bits are set in two nodes; NFCI

This was suggested in:
http://reviews.llvm.org/D13956

and is a follow-on to:
http://reviews.llvm.org/rL252515
http://reviews.llvm.org/rL252519

This lets us remove logically equivalent/duplicated code from DAGCombiner and X86ISelDAGToDAG.

A corresponding function for IR instructions already exists in ValueTracking.

llvm-svn: 252539

1 files changed, 5 insertions, 17 deletions

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 0cbeda91ccc..868ae4e19e5 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1338,29 +1338,17 @@ bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
       return false;
     break;
 
-  case ISD::OR: {
-    // TODO: The bit-checking logic should be put into a helper function and
-    // used by DAGCombiner.
-
+  case ISD::OR:
     // We want to look through a transform in InstCombine and DAGCombiner that
     // turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
-    APInt LHSZero, LHSOne;
-    APInt RHSZero, RHSOne;
-    CurDAG->computeKnownBits(N.getOperand(0), LHSZero, LHSOne);
-    CurDAG->computeKnownBits(N.getOperand(1), RHSZero, RHSOne);
-
-    // If we know that there are no common bits set by the operands of this
-    // 'or', it is equivalent to an 'add'. For example:
-    // (or (and x, 1), (shl y, 3)) --> (add (and x, 1), (shl y, 3))
+    // Example: (or (and x, 1), (shl y, 3)) --> (add (and x, 1), (shl y, 3))
     // An 'lea' can then be used to match the shift (multiply) and add:
     // and $1, %esi
     // lea (%rsi, %rdi, 8), %rax
-    if ((LHSZero | RHSZero).isAllOnesValue())
-      if (!matchAdd(N, AM, Depth))
-        return false;
-
+    if (CurDAG->haveNoCommonBitsSet(N.getOperand(0), N.getOperand(1)) &&
+        !matchAdd(N, AM, Depth))
+      return false;
     break;
-  }
 
   case ISD::AND: {
     // Perform some heroic transforms on an and of a constant-count shift