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| author | Andrey Turetskiy <andrey.turetskiy@gmail.com> | 2016-04-11 10:07:36 +0000 |
|---|---|---|
| committer | Andrey Turetskiy <andrey.turetskiy@gmail.com> | 2016-04-11 10:07:36 +0000 |
| commit | 9df334c28e35241e5971b086fd3b96d0a998e00c (patch) | |
| tree | 6bee172e3a5fa614bda57388ae9f3c84018fdd12 /llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | |
| parent | 036d0600448d6137300eb0bfcbf99a24e8632204 (diff) | |
| download | bcm5719-llvm-9df334c28e35241e5971b086fd3b96d0a998e00c.tar.gz bcm5719-llvm-9df334c28e35241e5971b086fd3b96d0a998e00c.zip | |
[X86] Restrict max long nop length for Lakemont.
Restrict the max length of long nops for Lakemont to 7. Experiments on MCU
benchmarks (Dhrystone, Coremark) show that this is the most optimal length.
Differential Revision: http://reviews.llvm.org/D18897
llvm-svn: 265924
Diffstat (limited to 'llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index def1b94a8ea..a91ab85a9a2 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -72,7 +72,8 @@ class X86AsmBackend : public MCAsmBackend { const uint64_t MaxNopLength; public: X86AsmBackend(const Target &T, StringRef CPU) - : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) { + : MCAsmBackend(), CPU(CPU), + MaxNopLength((CPU == "slm" || CPU == "lakemont") ? 7 : 15) { HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" && |
