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| author | Andrey Turetskiy <andrey.turetskiy@gmail.com> | 2016-04-11 10:07:36 +0000 |
|---|---|---|
| committer | Andrey Turetskiy <andrey.turetskiy@gmail.com> | 2016-04-11 10:07:36 +0000 |
| commit | 9df334c28e35241e5971b086fd3b96d0a998e00c (patch) | |
| tree | 6bee172e3a5fa614bda57388ae9f3c84018fdd12 | |
| parent | 036d0600448d6137300eb0bfcbf99a24e8632204 (diff) | |
| download | bcm5719-llvm-9df334c28e35241e5971b086fd3b96d0a998e00c.tar.gz bcm5719-llvm-9df334c28e35241e5971b086fd3b96d0a998e00c.zip | |
[X86] Restrict max long nop length for Lakemont.
Restrict the max length of long nops for Lakemont to 7. Experiments on MCU
benchmarks (Dhrystone, Coremark) show that this is the most optimal length.
Differential Revision: http://reviews.llvm.org/D18897
llvm-svn: 265924
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/MC/X86/x86_long_nop.s | 20 |
2 files changed, 13 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index def1b94a8ea..a91ab85a9a2 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -72,7 +72,8 @@ class X86AsmBackend : public MCAsmBackend { const uint64_t MaxNopLength; public: X86AsmBackend(const Target &T, StringRef CPU) - : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) { + : MCAsmBackend(), CPU(CPU), + MaxNopLength((CPU == "slm" || CPU == "lakemont") ? 7 : 15) { HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" && diff --git a/llvm/test/MC/X86/x86_long_nop.s b/llvm/test/MC/X86/x86_long_nop.s index eee840c5a97..806f841e891 100644 --- a/llvm/test/MC/X86/x86_long_nop.s +++ b/llvm/test/MC/X86/x86_long_nop.s @@ -2,7 +2,8 @@ # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=SLM %s +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s # Ensure alignment directives also emit sequences of 15-byte NOPs on processors # capable of using long NOPs. @@ -15,11 +16,12 @@ inc %eax # CHECK-NEXT: 1f: nop # CHECK-NEXT: 20: inc -# On Silvermont we emit only 7 byte NOPs since longer NOPs are not profitable -# SLM: 0: inc -# SLM-NEXT: 1: nop -# SLM-NEXT: 8: nop -# SLM-NEXT: f: nop -# SLM-NEXT: 16: nop -# SLM-NEXT: 1d: nop -# SLM-NEXT: 20: inc +# On Silvermont and Lakemont we emit only 7 byte NOPs since longer NOPs +# are not profitable. +# LNOP7: 0: inc +# LNOP7-NEXT: 1: nop +# LNOP7-NEXT: 8: nop +# LNOP7-NEXT: f: nop +# LNOP7-NEXT: 16: nop +# LNOP7-NEXT: 1d: nop +# LNOP7-NEXT: 20: inc |
