summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
diff options
context:
space:
mode:
authorDorit Nuzman <dorit.nuzman@intel.com>2018-10-31 09:57:56 +0000
committerDorit Nuzman <dorit.nuzman@intel.com>2018-10-31 09:57:56 +0000
commit34da6dd696439e195e7b650d97a95913101a88d9 (patch)
treea718d6a89ceb39ada3675f96f8de45c051e8ce7f /llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
parent889356eb719ded45c708514fb03777f705eb5934 (diff)
downloadbcm5719-llvm-34da6dd696439e195e7b650d97a95913101a88d9.tar.gz
bcm5719-llvm-34da6dd696439e195e7b650d97a95913101a88d9.zip
[LV] Support vectorization of interleave-groups that require an epilog under
optsize using masked wide loads Under Opt for Size, the vectorizer does not vectorize interleave-groups that have gaps at the end of the group (such as a loop that reads only the even elements: a[2*i]) because that implies that we'll require a scalar epilogue (which is not allowed under Opt for Size). This patch extends the support for masked-interleave-groups (introduced by D53011 for conditional accesses) to also cover the case of gaps in a group of loads; Targets that enable the masked-interleave-group feature don't have to invalidate interleave-groups of loads with gaps; they could now use masked wide-loads and shuffles (if that's what the cost model selects). Reviewers: Ayal, hsaito, dcaballe, fhahn Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D53668 llvm-svn: 345705
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h')
-rw-r--r--llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
index 347a8a632f0..406f075c8a6 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
@@ -93,7 +93,9 @@ public:
unsigned Factor,
ArrayRef<unsigned> Indices,
unsigned Alignment,
- unsigned AddressSpace, bool IsMasked = false);
+ unsigned AddressSpace,
+ bool UseMaskForCond = false,
+ bool UseMaskForGaps = false);
/// @}
};
OpenPOWER on IntegriCloud