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authorChris Lattner <sabre@nondot.org>2003-04-25 05:23:10 +0000
committerChris Lattner <sabre@nondot.org>2003-04-25 05:23:10 +0000
commitefbae9cff177368166f7fb9ccac0b8f16c4b401b (patch)
treeb775bce51a67ae5fe9bf181f0a2ad45596e3d1a9 /llvm/lib/Target/Sparc/SparcInstrInfo.cpp
parent21a7218c5f8909a7a8fefc856f298f401803535d (diff)
downloadbcm5719-llvm-efbae9cff177368166f7fb9ccac0b8f16c4b401b.tar.gz
bcm5719-llvm-efbae9cff177368166f7fb9ccac0b8f16c4b401b.zip
Fix obvious type-o
llvm-svn: 5932
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/Sparc/SparcInstrInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 6df7617c93e..8bdb0f29669 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -443,7 +443,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
if (opSize > destSize ||
(val->getType()->isSigned()
- && destSize < target.getTargetData().getIntegerRegize()))
+ && destSize < target.getTargetData().getIntegerRegSize()))
{ // operand is larger than dest,
// OR both are equal but smaller than the full register size
// AND operand is signed, so it may have extra sign bits:
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