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author | Chris Lattner <sabre@nondot.org> | 2003-04-25 05:23:10 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2003-04-25 05:23:10 +0000 |
commit | efbae9cff177368166f7fb9ccac0b8f16c4b401b (patch) | |
tree | b775bce51a67ae5fe9bf181f0a2ad45596e3d1a9 /llvm/lib | |
parent | 21a7218c5f8909a7a8fefc856f298f401803535d (diff) | |
download | bcm5719-llvm-efbae9cff177368166f7fb9ccac0b8f16c4b401b.tar.gz bcm5719-llvm-efbae9cff177368166f7fb9ccac0b8f16c4b401b.zip |
Fix obvious type-o
llvm-svn: 5932
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 2 | ||||
-rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrSelection.cpp | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 6df7617c93e..8bdb0f29669 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -443,7 +443,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target, if (opSize > destSize || (val->getType()->isSigned() - && destSize < target.getTargetData().getIntegerRegize())) + && destSize < target.getTargetData().getIntegerRegSize())) { // operand is larger than dest, // OR both are equal but smaller than the full register size // AND operand is signed, so it may have extra sign bits: diff --git a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp index 73e3b1ce6fa..50e2fe23d4d 100644 --- a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp @@ -759,7 +759,7 @@ CreateShiftInstructions(const TargetMachine& target, Value* shiftDest = destVal; unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType()); if ((shiftOpCode == SLL || shiftOpCode == SLLX) - && opSize < target.getTargetData().getIntegerRegize()) + && opSize < target.getTargetData().getIntegerRegSize()) { // put SLL result into a temporary shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp"); mcfi.addTemp(shiftDest); @@ -2305,7 +2305,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, .addReg(dest, MOTy::Def); mvec.push_back(M); } - else if (destSize < target.getTargetData().getIntegerRegize()) + else if (destSize < target.getTargetData().getIntegerRegSize()) assert(0 && "Unsupported type size: 32 < size < 64 bits"); } } |