summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Sparc/Disassembler
diff options
context:
space:
mode:
authorVenkatraman Govindaraju <venkatra@cs.wisc.edu>2014-03-02 03:39:39 +0000
committerVenkatraman Govindaraju <venkatra@cs.wisc.edu>2014-03-02 03:39:39 +0000
commit81aae572828077f54948b6dfdcab5003a4985ab9 (patch)
tree07d11385b9accc78a79b1d1569f84e0288ecbc1f /llvm/lib/Target/Sparc/Disassembler
parent871171a25beb46d128e0a5713d8fff18516191e7 (diff)
downloadbcm5719-llvm-81aae572828077f54948b6dfdcab5003a4985ab9.tar.gz
bcm5719-llvm-81aae572828077f54948b6dfdcab5003a4985ab9.zip
[Sparc] Add support for parsing fcmp with %fcc registers.
llvm-svn: 202610
Diffstat (limited to 'llvm/lib/Target/Sparc/Disassembler')
-rw-r--r--llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index e8314f23842..e01196cbccb 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -113,6 +113,9 @@ static const unsigned QFPRegDecoderTable[] = {
SP::Q6, SP::Q14, ~0U, ~0U,
SP::Q7, SP::Q15, ~0U, ~0U } ;
+static const unsigned FCCRegDecoderTable[] = {
+ SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
+
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@@ -174,6 +177,16 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo > 3)
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+
static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
OpenPOWER on IntegriCloud