From c6c4e8bd5aa536ee5513539a5d42e9743291f1dd Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Thu, 19 Oct 2017 21:43:29 +0000 Subject: [RISCV] Add missing hunk from r316188 r316188 didn't set guessInstructionProperties=1 as it should have done. llvm-svn: 316189 --- llvm/lib/Target/RISCV/RISCV.td | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/RISCV') diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index da919acad36..54aa570e13b 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -40,7 +40,9 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; //===----------------------------------------------------------------------===// def RISCVInstrInfo : InstrInfo { - let guessInstructionProperties = 0; + // TODO: disable guessInstructionProperties when + // https://reviews.llvm.org/D37065 lands. + let guessInstructionProperties = 1; } def RISCVAsmParser : AsmParser { -- cgit v1.2.3