diff options
author | Shiva Chen <shiva0217@gmail.com> | 2019-09-13 04:03:32 +0000 |
---|---|---|
committer | Shiva Chen <shiva0217@gmail.com> | 2019-09-13 04:03:32 +0000 |
commit | a49a16ddd0eb06cd0d84e2f073364397d94a1e84 (patch) | |
tree | 53673c3725546be72e56fc212238367911a8bbca /llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | |
parent | ea530ba3ed757de7ffc45114e9b5e9fa72475fe3 (diff) | |
download | bcm5719-llvm-a49a16ddd0eb06cd0d84e2f073364397d94a1e84.tar.gz bcm5719-llvm-a49a16ddd0eb06cd0d84e2f073364397d94a1e84.zip |
[RISCV] Support stack offset exceed 32-bit for RV64
Differential Revision: https://reviews.llvm.org/D61884
llvm-svn: 371810
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFrameLowering.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index ad19741a427..7d48634f206 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -74,7 +74,7 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB, .addReg(SrcReg) .addImm(Val) .setMIFlag(Flag); - } else if (isInt<32>(Val)) { + } else { unsigned Opc = RISCV::ADD; bool isSub = Val < 0; if (isSub) { @@ -83,13 +83,11 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB, } Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); - TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag); + TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag); BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) .addReg(SrcReg) .addReg(ScratchReg, RegState::Kill) .setMIFlag(Flag); - } else { - report_fatal_error("adjustReg cannot yet handle adjustments >32 bits"); } } |