diff options
| author | Shiva Chen <shiva0217@gmail.com> | 2019-09-13 04:03:24 +0000 |
|---|---|---|
| committer | Shiva Chen <shiva0217@gmail.com> | 2019-09-13 04:03:24 +0000 |
| commit | ea530ba3ed757de7ffc45114e9b5e9fa72475fe3 (patch) | |
| tree | 1bb1c4423bd4520052e4cdeac66ebb0ec5f1dc35 /llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | |
| parent | 67d9349dad3f4a950e6a389748feb028abb00537 (diff) | |
| download | bcm5719-llvm-ea530ba3ed757de7ffc45114e9b5e9fa72475fe3.tar.gz bcm5719-llvm-ea530ba3ed757de7ffc45114e9b5e9fa72475fe3.zip | |
Revert "[RISCV] Support stack offset exceed 32-bit for RV64"
This reverts commit 1c340c62058d4115d21e5fa1ce3a0d094d28c792.
llvm-svn: 371809
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 7d48634f206..ad19741a427 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -74,7 +74,7 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB, .addReg(SrcReg) .addImm(Val) .setMIFlag(Flag); - } else { + } else if (isInt<32>(Val)) { unsigned Opc = RISCV::ADD; bool isSub = Val < 0; if (isSub) { @@ -83,11 +83,13 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB, } Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); - TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag); + TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag); BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) .addReg(SrcReg) .addReg(ScratchReg, RegState::Kill) .setMIFlag(Flag); + } else { + report_fatal_error("adjustReg cannot yet handle adjustments >32 bits"); } } |
