diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 09:51:55 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 09:51:55 +0000 |
| commit | d590c85753be6742d170749734eb893f9fc1b5d5 (patch) | |
| tree | 1119d8035fb5b8e103e6821a27193745612a87f0 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | d80d6c5a56098efe7dd90e2fea6d49da87724251 (diff) | |
| download | bcm5719-llvm-d590c85753be6742d170749734eb893f9fc1b5d5.tar.gz bcm5719-llvm-d590c85753be6742d170749734eb893f9fc1b5d5.zip | |
[TableGen] Give the option of tolerating duplicate register names
A number of architectures re-use the same register names (e.g. for both 32-bit
FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated
MatchRegisterName and MatchRegisterAltName, as tablegen (when built with
asserts enabled) will fail.
When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register
names will be tolerated. A backend can then coerce registers to the desired
register class by (for instance) implementing validateTargetOperandClass.
At least the in-tree Sparc backend could benefit from this, as does RISC-V
(single and double precision floating point registers).
Differential Revision: https://reviews.llvm.org/D39845
llvm-svn: 320018
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions
