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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2018-10-04 21:44:32 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2018-10-04 21:44:32 +0000 |
| commit | ab358bfd0994b6c2b57e37be26869a611dc8fdd5 (patch) | |
| tree | 64f450fe2b8464602294cd16756be3b9ba87628a /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | bf378b808ae19fa709bb5babf5bcfd65a6688cb6 (diff) | |
| download | bcm5719-llvm-ab358bfd0994b6c2b57e37be26869a611dc8fdd5.tar.gz bcm5719-llvm-ab358bfd0994b6c2b57e37be26869a611dc8fdd5.zip | |
[globalisel][combine] Fix a rare crash when encountering an instruction whose op0 isn't a reg
The simplest instance of this is an intrinsic with no results which will have the
intrinsic ID as operand 0.
Also fix some benign incorrectness when op0 is a reg but isn't a def that was
guarded against by checking for the extension opcodes.
llvm-svn: 343821
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions
