diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2017-09-17 14:27:35 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-09-17 14:27:35 +0000 |
| commit | 6758ecb98cf6a1e2d99f6a53cffe7d4848371cbc (patch) | |
| tree | 685021fbf953e218b00c100278cfba3b4113bbfd /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 06335bbd2ff63e5f67790f26122c76aeae74f822 (diff) | |
| download | bcm5719-llvm-6758ecb98cf6a1e2d99f6a53cffe7d4848371cbc.tar.gz bcm5719-llvm-6758ecb98cf6a1e2d99f6a53cffe7d4848371cbc.zip | |
[RISCV] Add support for all RV32I instructions
This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).
Differential Revision: https://reviews.llvm.org/D23566
llvm-svn: 313485
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions
