R600: Add option to disable promote alloca

This can make writing some tests harder, so add a flag
to disable it.

llvm-svn: 212893

4 files changed, 24 insertions, 5 deletions

diff --git a/llvm/lib/Target/R600/AMDGPU.td b/llvm/lib/Target/R600/AMDGPU.td
index 6ff9ab7ab7d..89992c202ea 100644
--- a/llvm/lib/Target/R600/AMDGPU.td
+++ b/llvm/lib/Target/R600/AMDGPU.td
@@ -25,6 +25,11 @@ def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
         "false",
         "Disable IR Structurizer">;
 
+def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
+        "EnablePromoteAlloca",
+        "true",
+        "Enable promote alloca pass">;
+
 // Target features
 
 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp
index b83c290c1f0..d5203611756 100644
--- a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -16,6 +16,8 @@
 #include "R600InstrInfo.h"
 #include "SIInstrInfo.h"
 
+#include "llvm/ADT/SmallString.h"
+
 using namespace llvm;
 
 #define DEBUG_TYPE "amdgpu-subtarget"
@@ -37,12 +39,17 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS) :
   FP64(false),
   CaymanISA(false),
   EnableIRStructurizer(true),
+  EnablePromoteAlloca(false),
   EnableIfCvt(true),
   WavefrontSize(0),
   CFALUBug(false),
   LocalMemorySize(0),
   InstrItins(getInstrItineraryForCPU(GPU)) {
-  ParseSubtargetFeatures(GPU, FS);
+
+  SmallString<256> FullFS("+promote-alloca,");
+  FullFS += FS;
+
+  ParseSubtargetFeatures(GPU, FullFS);
 
   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
     InstrInfo.reset(new R600InstrInfo(*this));
diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.h b/llvm/lib/Target/R600/AMDGPUSubtarget.h
index 0c388b33872..68634ea883b 100644
--- a/llvm/lib/Target/R600/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/R600/AMDGPUSubtarget.h
@@ -52,6 +52,7 @@ private:
   bool FP64;
   bool CaymanISA;
   bool EnableIRStructurizer;
+  bool EnablePromoteAlloca;
   bool EnableIfCvt;
   unsigned WavefrontSize;
   bool CFALUBug;
@@ -81,7 +82,7 @@ public:
   }
 
   short getTexVTXClauseSize() const {
-      return TexVTXClauseSize;
+    return TexVTXClauseSize;
   }
 
   Generation getGeneration() const {
@@ -129,6 +130,10 @@ public:
     return EnableIRStructurizer;
   }
 
+  bool isPromoteAllocaEnabled() const {
+    return EnablePromoteAlloca;
+  }
+
   bool isIfCvtEnabled() const {
     return EnableIfCvt;
   }
diff --git a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
index 8aab94446b5..6a78b177e96 100644
--- a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -33,7 +33,6 @@
 #include "llvm/Transforms/Scalar.h"
 #include <llvm/CodeGen/Passes.h>
 
-
 using namespace llvm;
 
 extern "C" void LLVMInitializeR600Target() {
@@ -137,8 +136,11 @@ void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
 
 void AMDGPUPassConfig::addCodeGenPrepare() {
   const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
-  addPass(createAMDGPUPromoteAlloca(ST));
-  addPass(createSROAPass());
+  if (ST.isPromoteAllocaEnabled()) {
+    addPass(createAMDGPUPromoteAlloca(ST));
+    addPass(createSROAPass());
+  }
+
   TargetPassConfig::addCodeGenPrepare();
 }