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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-01-14 15:42:31 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-01-14 15:42:31 +0000 |
| commit | 42fb60e1a7d4b21d7e2ca68a8520954bedabcf21 (patch) | |
| tree | ad80eeea7e90812c8a85ccb831abc1d5dde66eae /llvm/lib/Target/R600/SIMachineFunctionInfo.cpp | |
| parent | d657321aefb4ff35078811332bd3d90aefbd564f (diff) | |
| download | bcm5719-llvm-42fb60e1a7d4b21d7e2ca68a8520954bedabcf21.tar.gz bcm5719-llvm-42fb60e1a7d4b21d7e2ca68a8520954bedabcf21.zip | |
R600/SI: Spill VGPRs to scratch space for compute shaders
llvm-svn: 225988
Diffstat (limited to 'llvm/lib/Target/R600/SIMachineFunctionInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIMachineFunctionInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp b/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp index d58f31db508..198dd568374 100644 --- a/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp @@ -29,6 +29,7 @@ void SIMachineFunctionInfo::anchor() {} SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) : AMDGPUMachineFunction(MF), TIDReg(AMDGPU::NoRegister), + HasSpilledVGPRs(false), PSInputAddr(0), NumUserSGPRs(0), LDSWaveSpillSize(0) { } @@ -50,7 +51,7 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( struct SpilledReg Spill; if (!LaneVGPRs.count(LaneVGPRIdx)) { - unsigned LaneVGPR = TRI->findUnusedVGPR(MRI); + unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass); LaneVGPRs[LaneVGPRIdx] = LaneVGPR; MRI.setPhysRegUsed(LaneVGPR); |
