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| author | Eric Christopher <echristo@gmail.com> | 2015-03-11 18:43:21 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2015-03-11 18:43:21 +0000 |
| commit | 6c5b511b4dd70fe47ad1f3e421bc231a90d6ee9b (patch) | |
| tree | de417ef956b29b7ea2d3a902acd81af2ef4ff28d /llvm/lib/Target/R600/AMDGPUInstrInfo.cpp | |
| parent | f4d9a5a964f64222f51c3b8b494588593f18eceb (diff) | |
| download | bcm5719-llvm-6c5b511b4dd70fe47ad1f3e421bc231a90d6ee9b.tar.gz bcm5719-llvm-6c5b511b4dd70fe47ad1f3e421bc231a90d6ee9b.zip | |
Remove the need to cache the subtarget in the R600 TargetRegisterInfo
classes.
llvm-svn: 231954
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUInstrInfo.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp b/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp index 28c15764c2f..f0f10ca5972 100644 --- a/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -31,7 +31,7 @@ using namespace llvm; void AMDGPUInstrInfo::anchor() {} AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st) - : AMDGPUGenInstrInfo(-1,-1), RI(st), ST(st) { } + : AMDGPUGenInstrInfo(-1, -1), ST(st) {} const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { return RI; @@ -356,8 +356,8 @@ static enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) { } int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const { - int MCOp = AMDGPU::getMCOpcode(Opcode, - AMDGPUSubtargetToSISubtarget(RI.ST.getGeneration())); + int MCOp = AMDGPU::getMCOpcode( + Opcode, AMDGPUSubtargetToSISubtarget(ST.getGeneration())); // -1 means that Opcode is already a native instruction. if (MCOp == -1) |
