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authorTom Stellard <thomas.stellard@amd.com>2013-07-30 14:31:03 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-07-30 14:31:03 +0000
commitaa313d0a744b3f0a8073a231deb6b6dfa6e441e4 (patch)
treee7cdb1e6c4b765d03077e7dc4c54c3d3fcf8b43a /llvm/lib/Target/R600/AMDGPUISelLowering.cpp
parent9744ffd652e02b83968178cb3cfa823a1ccbee57 (diff)
downloadbcm5719-llvm-aa313d0a744b3f0a8073a231deb6b6dfa6e441e4.tar.gz
bcm5719-llvm-aa313d0a744b3f0a8073a231deb6b6dfa6e441e4.zip
R600/SI: Expand vector fp <-> int conversions
llvm-svn: 187421
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUISelLowering.cpp')
-rw-r--r--llvm/lib/Target/R600/AMDGPUISelLowering.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
index 779d97f1776..16943870cdd 100644
--- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -101,13 +101,17 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
//Expand the following operations for the current type by default
setOperationAction(ISD::ADD, VT, Expand);
setOperationAction(ISD::AND, VT, Expand);
+ setOperationAction(ISD::FP_TO_SINT, VT, Expand);
+ setOperationAction(ISD::FP_TO_UINT, VT, Expand);
setOperationAction(ISD::MUL, VT, Expand);
setOperationAction(ISD::OR, VT, Expand);
setOperationAction(ISD::SHL, VT, Expand);
+ setOperationAction(ISD::SINT_TO_FP, VT, Expand);
setOperationAction(ISD::SRL, VT, Expand);
setOperationAction(ISD::SRA, VT, Expand);
setOperationAction(ISD::SUB, VT, Expand);
setOperationAction(ISD::UDIV, VT, Expand);
+ setOperationAction(ISD::UINT_TO_FP, VT, Expand);
setOperationAction(ISD::UREM, VT, Expand);
setOperationAction(ISD::VSELECT, VT, Expand);
setOperationAction(ISD::XOR, VT, Expand);
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