From aa313d0a744b3f0a8073a231deb6b6dfa6e441e4 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 30 Jul 2013 14:31:03 +0000 Subject: R600/SI: Expand vector fp <-> int conversions llvm-svn: 187421 --- llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/Target/R600/AMDGPUISelLowering.cpp') diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 779d97f1776..16943870cdd 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -101,13 +101,17 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : //Expand the following operations for the current type by default setOperationAction(ISD::ADD, VT, Expand); setOperationAction(ISD::AND, VT, Expand); + setOperationAction(ISD::FP_TO_SINT, VT, Expand); + setOperationAction(ISD::FP_TO_UINT, VT, Expand); setOperationAction(ISD::MUL, VT, Expand); setOperationAction(ISD::OR, VT, Expand); setOperationAction(ISD::SHL, VT, Expand); + setOperationAction(ISD::SINT_TO_FP, VT, Expand); setOperationAction(ISD::SRL, VT, Expand); setOperationAction(ISD::SRA, VT, Expand); setOperationAction(ISD::SUB, VT, Expand); setOperationAction(ISD::UDIV, VT, Expand); + setOperationAction(ISD::UINT_TO_FP, VT, Expand); setOperationAction(ISD::UREM, VT, Expand); setOperationAction(ISD::VSELECT, VT, Expand); setOperationAction(ISD::XOR, VT, Expand); -- cgit v1.2.3