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authorJoerg Sonnenberger <joerg@bec.de>2014-08-05 13:34:01 +0000
committerJoerg Sonnenberger <joerg@bec.de>2014-08-05 13:34:01 +0000
commit9dedceb71d96256f906669e2c616034e23362dbe (patch)
tree79e2c2899bfffe4f2ee07654ad71c7be59301590 /llvm/lib/Target/PowerPC
parent05756947290e5a539991c6ae08dd09fd0c62fd67 (diff)
downloadbcm5719-llvm-9dedceb71d96256f906669e2c616034e23362dbe.tar.gz
bcm5719-llvm-9dedceb71d96256f906669e2c616034e23362dbe.zip
Add lswi / stswi for assembler use with a warning to not add patterns
for them. llvm-svn: 214862
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index cf20baea5b4..dda017981b0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3037,6 +3037,16 @@ def : Pat<(i1 (not (trunc i64:$in))),
// PowerPC Instructions used for assembler/disassembler only
//
+// FIXME: For B=0 or B > 8, the registers following RT are used.
+// WARNING: Do not add patterns for this instruction without fixing this.
+def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
+ "lswi $RT, $A, $B", IIC_LdStLoad, []>;
+
+// FIXME: For B=0 or B > 8, the registers following RT are used.
+// WARNING: Do not add patterns for this instruction without fixing this.
+def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
+ "stswi $RT, $A, $B", IIC_LdStLoad, []>;
+
def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
"isync", IIC_SprISYNC, []>;
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