diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 10 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt | 5 | ||||
| -rw-r--r-- | llvm/test/MC/PowerPC/ppc64-encoding-ext.s | 7 |
3 files changed, 22 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index cf20baea5b4..dda017981b0 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -3037,6 +3037,16 @@ def : Pat<(i1 (not (trunc i64:$in))), // PowerPC Instructions used for assembler/disassembler only // +// FIXME: For B=0 or B > 8, the registers following RT are used. +// WARNING: Do not add patterns for this instruction without fixing this. +def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B), + "lswi $RT, $A, $B", IIC_LdStLoad, []>; + +// FIXME: For B=0 or B > 8, the registers following RT are used. +// WARNING: Do not add patterns for this instruction without fixing this. +def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B), + "stswi $RT, $A, $B", IIC_LdStLoad, []>; + def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), "isync", IIC_SprISYNC, []>; diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt index 45f4d3e045e..7d780e232ee 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt @@ -2266,3 +2266,8 @@ # CHECK: tlbia 0x7c 0x00 0x02 0xe4 + +# CHECK: lswi 8, 6, 7 +0x7d 0x06 0x3c 0xaa +# CHECK: stswi 8, 6, 7 +0x7d 0x06 0x3d 0xaa diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s index 99a698d3a55..56a825dc35c 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s @@ -3609,3 +3609,10 @@ # CHECK-BE: tlbia # encoding: [0x7c,0x00,0x02,0xe4] # CHECK-LE: tlbia # encoding: [0xe4,0x02,0x00,0x7c] tlbia + +# CHECK-BE: lswi 8, 6, 7 # encoding: [0x7d,0x06,0x3c,0xaa] +# CHECK-LE: lswi 8, 6, 7 # encoding: [0xaa,0x3c,0x06,0x7d] + lswi %r8, %r6, 7 +# CHECK-BE: stswi 8, 6, 7 # encoding: [0x7d,0x06,0x3d,0xaa] +# CHECK-LE: stswi 8, 6, 7 # encoding: [0xaa,0x3d,0x06,0x7d] + stswi %r8, %r6, 7 |
