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| author | Dale Johannesen <dalej@apple.com> | 2007-10-14 01:58:32 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2007-10-14 01:58:32 +0000 |
| commit | 2f6b6d6fb0022d020d09e8197fe9b645c0184837 (patch) | |
| tree | 321669422faa97dbbed3a1ee993c58e7ec9f30fa /llvm/lib/Target/PowerPC | |
| parent | 19db093b350f2050a91bc7df7f548272453fd2ee (diff) | |
| download | bcm5719-llvm-2f6b6d6fb0022d020d09e8197fe9b645c0184837.tar.gz bcm5719-llvm-2f6b6d6fb0022d020d09e8197fe9b645c0184837.zip | |
Fix type mismatch error in PPC Altivec (only causes
a problem when asserts are on). From vecLib.
llvm-svn: 42959
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index bd43d497d2d..9ef8f0ebc0d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2570,14 +2570,14 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { if (SextVal >= 0 && SextVal <= 31) { SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); - LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); + LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); } // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). if (SextVal >= -31 && SextVal <= 0) { SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); - LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); + LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); } } |
