Fix type mismatch error in PPC Altivec (only causes

a problem when asserts are on).  From vecLib.

llvm-svn: 42959

1 files changed, 2 insertions, 2 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index bd43d497d2d..9ef8f0ebc0d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2570,14 +2570,14 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
     if (SextVal >= 0 && SextVal <= 31) {
       SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
       SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
-      LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
+      LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
       return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
     }
     // Odd, in range [-31,-17]:  (vsplti C)+(vsplti -16).
     if (SextVal >= -31 && SextVal <= 0) {
       SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
       SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
-      LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
+      LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
       return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
     }
   }