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authorHal Finkel <hfinkel@anl.gov>2013-03-23 22:06:03 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-23 22:06:03 +0000
commitcc1eeda16d5cb9ef37d3ffa226b8c0ff3616e2ca (patch)
tree4db7420acf354a97ea45a9a6f8adc393e99028cf /llvm/lib/Target/PowerPC/PPCInstrInfo.h
parentc2bdf1973b2930e1c2f75350632bb91616b89614 (diff)
downloadbcm5719-llvm-cc1eeda16d5cb9ef37d3ffa226b8c0ff3616e2ca.tar.gz
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Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. llvm-svn: 177832
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.h')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 5d4ae915b45..635e3480b06 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -72,12 +72,12 @@ class PPCInstrInfo : public PPCGenInstrInfo {
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs,
- bool &NonRI) const;
+ bool &NonRI, bool &SpillsVRS) const;
bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs,
- bool &NonRI) const;
+ bool &NonRI, bool &SpillsVRS) const;
public:
explicit PPCInstrInfo(PPCTargetMachine &TM);
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