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| author | Keno Fischer <kfischer@college.harvard.edu> | 2016-06-01 20:31:07 +0000 |
|---|---|---|
| committer | Keno Fischer <kfischer@college.harvard.edu> | 2016-06-01 20:31:07 +0000 |
| commit | 5573483c5bfff1fe65816efa34941e62998aefdb (patch) | |
| tree | ed96579d88753c6966f0469d25dcf66fe5a903dd /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | 0c09517867cf18cdb5626e33500660317a27f675 (diff) | |
| download | bcm5719-llvm-5573483c5bfff1fe65816efa34941e62998aefdb.tar.gz bcm5719-llvm-5573483c5bfff1fe65816efa34941e62998aefdb.zip | |
[PPC64] Fix SUBFC8 Defs list
Fix PR27943 "Bad machine code: Using an undefined physical register".
SUBFC8 implicitly defines the CR0 register, but this was omitted in
the instruction definition.
Patch by Jameson Nash <jameson@juliacomputing.com>
Reviewers: hfinkel
Differential Revision: http://reviews.llvm.org/D20802
llvm-svn: 271425
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 313ab8846ad..9d8e29c462c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1795,6 +1795,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, MI->addOperand(*MI->getParent()->getParent(), MachineOperand::CreateReg(*ImpUses, false, true)); } + assert(MI->definesRegister(PPC::CR0) && + "Record-form instruction does not define cr0?"); // Modify the condition code of operands in OperandsToUpdate. // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to |
